1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, a manufacturing method thereof and a method of programming information into the memory, in particular, to a nonvolatile semiconductor memory device capable of performing electrical writing and erasure of information, a manufacturing method thereof and a method of programming information into the memory device.
2. Description of the Related Art
A nonvolatile semiconductor memory device which programs information using channel hot electrons and erases information using an FN (Fowler-Nordheim) tunneling current has been conventionally provided (Refer to U.S. Pat. No. 6,265,266 (hereinafter referred to as a known document 1), for example). FIG. 6 is a schematic sectional view of a memory cell of a nonvolatile semiconductor memory device described in the known document 1.
In the nonvolatile semiconductor memory device 90 having a conventional configuration as shown in FIG. 6, second conductive type (hereinafter referred to as an “N-type”) of impurity diffusion areas 3, 4, and 91 are formed on a first conductive type of (hereinafter referred to as an “P-type”) semiconductor substrate 2. A first insulating film 5 is deposited in the area sandwiched between the impurity diffusion area 91 and the impurity diffusion area 4 on the semiconductor substrate 2. A charge storage layer 6, a third insulating film 7 and a first gate electrode 8 are formed on the first insulating film 5 in this order. On the other hand, a second insulating film 9 is deposited in the area sandwiched between the impurity diffusion area 3 and the impurity diffusion area 91 on the semiconductor substrate 2. A second gate electrode 10 is formed on the second insulating film 9. The impurity diffusion area 91 is described to be in a high-density impurity state having the range of 2×1015 to 6×1015 ions/cm2.
With such configuration, the impurity diffusion area 3, the second insulating film 9, the second gate electrode 10 and the impurity diffusion area 91 form one transistor (hereinafter referred to as an “access transistor”) 11. The impurity diffusion area 91, the second insulating film 5, the charge storage layer 6, the third insulating film 7, the first gate electrode 8 and the impurity diffusion area 4 form another transistor (hereinafter referred to as a “memory cell transistor”) 12. The access transistor 11 is serially connected to the memory cell transistor 12 via the impurity diffusion area 91. The impurity diffusion area 4 is connected to a drain bit line and the impurity diffusion area 3 is connected to a source bit line.
An example of a method of driving the nonvolatile semiconductor memory device 90 thus constituted will be described. In an example of a programming method, a predetermined positive voltage is applied to the first gate electrode 8, the second gate electrode 10 and the impurity diffusion area 4 as a drain of a selected memory cell respectively, and the impurity diffusion area 3 as a source is connected to a ground voltage. At this time, a channel area is formed in each of portions under the first gate electrode 8 and the second gate electrode 10 on the semiconductor substrate 2. Thus, the access transistor 11 and the memory cell transistor 12 are put into a conductive state. At this time, since a pinch-off point where channel disappears occurs in the vicinity of the drain of the impurity diffusion area 91 and electrons drift through the point, a high electrical field is generated in the area near the drain due to a high potential difference between channel potential and drain potential. Since a positive voltage is applied to the first gate electrode 8, channel hot electrons are drawn toward the first gate electrode 8 and taken into the charge storage layer 6 so that information may be programmed. As described above, since it is necessary to concentrate the high potential difference on the portion near the drain and prevent voltage drop in the other areas as much as possible, the impurity density in the impurity diffusion area 91 must be high.
In an example of an erasing method, the impurity diffusion area 3 is opened and a predetermined negative voltage is applied to the second gate electrode 10 and the first gate electrode 8. A predetermined positive voltage is applied to the impurity diffusion area 4. As a result, a high potential difference occurs between the first gate electrode 8 and the impurity diffusion area 4, thereby generating a high electrical field between them. The high electrical field generates a current (FN current) tunneling through the first insulating film 5 to pull out the electrons held in the charge storage layer 6 toward the impurity diffusion area 4. Thus, stored information is erased.
In an example of a reading method, by applying a positive voltage to the impurity diffusion area 4, the first gate electrode 8 and the second gate electrode 10 and grounding the impurity diffusion area 3, current amount passing through the source line is detected. When information is stored in the memory cell transistor 12, electrons are held in the charge storage layer 6. Thus, compared with an initial state (no electrons are held in the charge storage layer 6, that is, no information is stored), a threshold voltage of the memory cell transistor 12 rises. In other words, since the current amount passing through the selected memory cell transistor 12 varies depending on whether information is stored in the memory cell transistor 12 or not, it is possible to determine whether information is programmed into the memory cell or not by detecting the current amount from the source line.
However, according to the nonvolatile semiconductor memory device described in the known document 1, information is programmed by injecting channel hot electrons. Thus, in programming, the current amount of 100 μA or more per memory cell and high voltage applied to the impurity diffusion area 4 serving as the drain are required. This is because it is necessary to give enough energy to cross an energy barrier of the first insulating film 5 to the electrons by forming a pinch-off area in the vicinity of impurity diffusion area 4 to constitute a high electrical field state and thus increasing the speed of electrons moving in the channel within the high electrical field in the pinch-off area. However, according to this method, energy necessary for crossing the energy barrier of the first insulating film 5 is given to the electrons, resulting in that excessive energy is given to the electrons with high voltage between the drain and the source. For this reason, the above-mentioned large current amount is needed. As a result, disadvantageously, injection efficiency becomes low.
In consideration with this, a nonvolatile semiconductor device capable of improving injection efficiency by adding a certain characteristic to configuration has been conventionally provided (Refer to, for example, Japanese Patent No. 2862434 (hereinafter referred to as a known document 2) and U.S. Pat. No. 5,212,541 (hereinafter referred to as a known document 3).
FIGS. 7A and 7B are schematic sectional views of a memory cell of a nonvolatile semiconductor memory device having conventional configuration described in the known document 2 and the known document 3. FIG. 7A shows the memory cell described in the known document 2 and FIG. 7B shows the memory cell described in the known document 3.
As shown in FIG. 7A, in a memory cell 94 having conventional configuration described in the known document 2, the second gate electrode 10 and the charge storage layer 6 in the form of a side spacer are formed between the impurity diffusion area 4 as a drain and the impurity diffusion area 3 as a source. A first gate electrode 8 is formed so as to cover these elements.
As shown in FIG. 7B, in a memory cell 95 having conventional configuration described in the known document 3, a part of the second gate electrode 10 extends above the first gate electrode 8 between the impurity diffusion area 4 as a drain and the impurity diffusion area 3 as a source. Thus, the gate electrodes in the area constitute a two-layer structure in which the first gate electrode 8 is situated next to a part of the second gate electrode 10 on the side wall of the first gate electrode 8 via an insulating film.
With such configuration as shown in FIG. 7A or 7B, in a state where a positive voltage is applied to the impurity diffusion area 4 as the drain and the impurity diffusion area 3 as the source is connected to a ground voltage, a positive voltage is applied to the second gate electrode 10 and the first gate electrode 8 in this order. A channel formed in an area under the second gate electrode 10 is put into a weak inversion state by applying the positive voltage to the second gate electrode 10 and a channel formed in an area under the first gate electrode 8 is put into a strong inversion state by applying the positive voltage to the first gate electrode 8. Since a high electrical field occurs in the vicinity of these boundaries, electrons fed from the side of the source (impurity diffusion area 3) are excited in this high electrical field and injected to the charge storage layer 6 from the source, thereby programming information (source-side injection). As compared with the method described in the known document 1, this method enables injection efficiency to be improved by about one digit.
However, in both the configurations described in the known document 2 and the known document 3, as shown in FIG. 7A or 7B, disadvantageously, two-layer gate materials are deposited so that the first gate electrode 8 may be situated next to a part of the second gate electrode 10 on the side wall of the first gate electrode 8 via an insulating film, resulting in a complicated manufacturing process. When the first and second gate electrodes are formed on the same layer to simplify the manufacturing process, the distance between the first and second gate electrodes becomes too large. Thus, it becomes difficult to control the inversion state of the surface of the first conductive type of semiconductor substrate in the area between the gate electrodes. As a result, since minority carrier density is greatly lowered, the current necessary for programming cannot be disadvantageously ensured.